Efficient modeling of switch-level networks containing undetermined logic node states
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 17 references indexed in Scilit:
- Magnitude classes in switch-level modelingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An algebra for switch-level simulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Switch-level simulation using dynamic graph algorithmsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- Automatic modeling of switch-level networks using partial orders (MOS circuits)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- Logic simulation with current-limited switchesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- A mixed-level MOS logic simulator utilizing a new continuous strength algebra (CSAL)Published by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- Self-Adjusting Networks for VLSI SimulationIEEE Transactions on Computers, 1987
- Fully Dynamic Switch-Level Simulation of CMOS CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- A Survey of Switch-Level AlgorithmsIEEE Design & Test of Computers, 1987
- Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay ModelingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983