Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds
Top Cited Papers
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
In order to simulate the effects of bridging faults correctly it is necessary to take into account the fact that not all gate inputs have the same logic threshold. This paper presents a general technique which can be used to determine if a particular structure of transistors gives rise to a bridge voltage which is higher or lower than a given threshold, in most cases without requiring circuit simulation. If desired, the technique can also be used to predict actual voltages, which agree well with SPICE simulations. The approach is substantially faster than previous approaches for accurately simulating bridging faults.Keywords
This publication has 12 references indexed in Scilit:
- Fault Model Evolution For Diagnosis: Accuracy vs PrecisionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A Comparison of Defect Models for Fault Location with Iddq MeasurementsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Detecting bridging faults with stuck-at test setsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Algorithms for current monitor based diagnosis of bridging and leakage faultsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Testing for parametric faults in static CMOS circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Diagnosing CMOS bridging faults with stuck-at fault dictionariesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- CMOS bridging fault detectionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- E-PROOFS: A CMOS bridging fault simulatorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Quiescent power supply current measurement for CMOS IC defect detectionIEEE Transactions on Industrial Electronics, 1989
- Fault Modeling and Logic Simulation of CMOS and MOS Integrated CircuitsBell System Technical Journal, 1978