IDDQ defect detection in deep submicron CMOS ICs

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Abstract
Traditional testing is based on applying signals to circuit inputs and observing logic stale of outputs. However, with the introduction of CMOS technology a new test technique emerged, that is based on applying signal inputs and observing standby electrical current. This technique is known as IDDQ testing. In most CMOS circuits, when all inputs are frozen in place and circuit transient activities settle down, the current drops by 3-5 orders of magnitude below normal levels. During testing, if there is a deviation from this behavior a defect is detected. While parametric test of electric current has always been popular (including in bipolar and NMOS technologies) to detect a short between power supply lines, the promise of IDDQ test is that it will also allow detection of bridging between signal nets and transistor stuck-on faults in CMOS circuits. However, in reality, the resolution of the size of the defect is limited by the magnitude of stand-by current. Since normal process variation can cause a shift in stand-by current by two orders of magnitude, choosing a single threshold for IDDQ defect detection is impractical. Many ideas have been proposed to overcome this problem, most of which are based on choosing an adaptive cut-off point for a wafer, or a lot. In this paper, we suggest a technique, that in concept, is akin to setting an individual cutoff point for a die. The concept has been validated based on actual data.

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