Overview of bus-based system-on-chip interconnections
- 25 June 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper introduces the basic properties, such as structure, transfer properties and arbitration of bus-based interconnections for System-on-Chip (SoC) designs. The overview shows that contemporary SoC buses differ only in minor details. As a result, practically every studied interconnection method could rather easily conform to a common interface. Such an interface would enhance design re-use and make system design easier. However, due to their similarity, the choice between buses is not a straightforward task.Keywords
This publication has 8 references indexed in Scilit:
- An efficient bus architecture for system-on-chip designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Asynchronous macrocell interconnect using MARBLEPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Modeling bus scheduling policies for real-time systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- LOTTERYBUS: a new high-performance communication architecture for system-on-chip designsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- ASOC: a scalable, single-chip communications architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Performance analysis of systems with multi-channel communication architecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- How VSIA answers the SOC dilemmaComputer, 1999
- Reconfiguration mechanism for an IP block based interconnectionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1999