Using ATPG for clock rules checking in complex scan designs

This publication has 18 references indexed in Scilit:

• Code generation and analysis for the functional verification of microprocessors
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Perturb And Simplify: Multi-level Boolean Network Optimizer
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Testing "untestable" faults in three-state circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Lean integration: achieving a quantum leap in performance and cost of logic LSIs
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• TDRC-a symbolic simulation based design for testability rules checker
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Extracting RTL models from transistor netlists
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Switch-level modeling of transistor-level stuck-at faults
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Automatic clock abstraction from sequential circuits
  Published by Association for Computing Machinery (ACM) ,1995
• Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
• SOCRATES: a highly efficient automatic test pattern generation system
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988