Circular BIST with partial scan
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A BIST (built-in self test) methodology that uses the circular BIST technique to perform a random test of sequential logic circuits is presented. The fault coverage obtained using this technique is supplemented by deterministic tests that are presented to the CUT (circuit under test) by configuring the circular path as a partial scan chain. A CAD (computer-aided-design) tool for automating this methodology is described, a variety of heuristics for picking which flip-flops should be included in the circular path are evaluated, and experimental results are presented.Keywords
This publication has 9 references indexed in Scilit:
- Effectiveness of fault detection for low-overhead self-testing VLSI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An automated BIST approach for general sequential logic synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Pseudorandom TestingIEEE Transactions on Computers, 1987
- Circular self-test path: a low-cost BIST techniquePublished by Association for Computing Machinery (ACM) ,1987
- Testability: Barriers to AcceptanceIEEE Design & Test of Computers, 1986
- On Random Pattern Test LengthIEEE Transactions on Computers, 1984
- Design for testability—A surveyProceedings of the IEEE, 1983
- Controllability/observability analysis of digital circuitsIEEE Transactions on Circuits and Systems, 1979
- The Error Latency of a Fault in a Sequential Digital CircuitIEEE Transactions on Computers, 1976