An adaptive timing-driven layout for high speed VLSI

This publication has 8 references indexed in Scilit:

• Critical path issue in VLSI design
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Predictive tools in VLSI system design: timing aspects
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Performance-driven placement of cell based IC's
  Published by Association for Computing Machinery (ACM) ,1989
• ORCA a sea-of-gates place and route system
  Published by Association for Computing Machinery (ACM) ,1989
• Algorithms for physical design of ‘sea-of-gates’ chips
  Computer-Aided Design, 1988
• Efficient Placement Algorithms Optimizing Delay for High-Speed ECL Masterslice LSI's
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1986
• Timing Influenced Layout Design
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1985
• An Algorithm for Path Connections and Its Applications
  IEEE Transactions on Electronic Computers, 1961