Low-power embedded SRAM modules with expanded margins for writing
- 30 August 2005
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- A transregional CMOS SRAM with single, logic V/sub DD/ and dynamic power railsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Universal-Vdd 0.65-2.0V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cellPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Static-noise margin analysis of MOS SRAM cellsIEEE Journal of Solid-State Circuits, 1987