Hardware assist for distributed shared memory
- 30 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1, 246-255
- https://doi.org/10.1109/icdcs.1993.287702
Abstract
No abstract availableKeywords
This publication has 23 references indexed in Scilit:
- Evaluating The Performance Of Four Snooping Cache Coherency ProtocolsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A characterization of sharing in parallel programs and its application to coherency protocol evaluationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The Wisconsin Multicube: a new large-scale cache-coherent multiprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Memory consistency and event ordering in scalable shared-memory multiprocessorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Hiding shared memory reference latency on the Galactica Net distributed shared memory architectureJournal of Parallel and Distributed Computing, 1992
- Paradigm: a highly scalable shared-memory multicomputer architectureComputer, 1991
- Memory access dependencies in shared-memory multiprocessorsIEEE Transactions on Software Engineering, 1990
- The implementation of a coherent memory abstraction on a NUMA multiprocessor: experiences with platinumPublished by Association for Computing Machinery (ACM) ,1989
- Hierarchical cache/bus architecture for shared memory multiprocessorsPublished by Association for Computing Machinery (ACM) ,1987
- The torus routing chipDistributed Computing, 1986