An embedded 32-b microprocessor core for low-power and high-performance applications

Publisher Website
Google Scholar
Abstract
An embedded RISC microprocessor core fabricated in a six-layer metal 0.18-/spl mu/m CMOS process implementing the ARM/sup TM/ V.5TE instruction set is described. The core described is the first implementation of the Intel XScale Microarchitecture/sup TM/. The microprocessor core, which includes caches, memory management units, and a bus controller, comprises a hard-embedded block 16.77 mm/sup 2/ in size. The implementation is primarily custom logic in a variety of circuit styles. The processor dissipates 450 mW at 1.3 V, 600 MHz, and scales between 55 mW at 0.7 V, 200 MHz, and 900 mW at 1.65 V 800 MHz. Architectural performance is 1000 MIPS at 800 MHz with efficiency ranging from over 850 MIPS/W at 1.65 V to over 4500 MIPS/W at 0.75 V. Architectural and circuit design approaches for low power and high performance are described and measured results from the initial implementation are shown. The first implementation VLSI chip has a 3.3-V pin interface and supports a 0.75-1.65-V core voltage range.

This publication has 5 references indexed in Scilit: