Advanced 5K-gate bipolar gate array with a 267 ps basic gate delay
- 1 December 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 19 (6) , 1038-1041
- https://doi.org/10.1109/jssc.1984.1052263
Abstract
To improve performance compared with a previously developed 5K-gate gate array, advanced process technology is used. A 47% smaller emitter window opening technique is used which results in an approximately 0.7-/spl mu/m-wide emitter. Furthermore, the speed-up capacitance of the basic nonthreshold logic cell is increased by 33% over that of the earlier gate array. Consequently, a 17% shorter gate delay of 267 ps, a 22-ps fan-out delay, and a 72-ps/mm load wire delay are achieved with under 1 mW power.Keywords
This publication has 2 references indexed in Scilit:
- A 5K-gate bipolar masterslice LSI with a 500 ps loaded gate delayIEEE Journal of Solid-State Circuits, 1983
- A 3-ns 1-kbit RAM using super self-aligned process technologyIEEE Journal of Solid-State Circuits, 1981