A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems
- 1 April 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 14 (2) , 312-318
- https://doi.org/10.1109/JSSC.1979.1051180
Abstract
A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are /spl plusmn/1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 /spl mu/AV/SUP -2/. The bipolar transistors have a low-resistance base contact. Current gain can be set independently. For current gain=90, the Early voltage if V/SUB A/=110 V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.Keywords
This publication has 6 references indexed in Scilit:
- A compatible NMOS, CMOS metal gate processIEEE Transactions on Electron Devices, 1978
- Experimental study of Gummel-Poon model parameter correlations for bipolar junction transistorsIEEE Journal of Solid-State Circuits, 1977
- Transistors with boron bases predeposited by ion implantation and annealed in various oxygen ambientsIEEE Transactions on Electron Devices, 1977
- Advanced compatible LSI process for N-MOS, CMOS and bipolar transistorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977
- CMOS process for high-performance analog LSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1976
- Fully ion-implanted bipolar transistorsIEEE Transactions on Electron Devices, 1974