A 3-ghz 25-mw Cmos Phase-locked Loop
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Thedemand forhigh-speed, low-power communication cir-cuitshasdramatically grown over thepast few years. Poten-tial markets from powerful personal communicators to wireless ATM systems have stimulated great effort in reducing the sup-ply voltage and power dissipation of gigahertzcircuits. Inthis respect, deep submicron CMOS technologies have become con-tendersto 111-V and silicon bipolardevices becausethey offer the speed, density, and power requiredfor suchapplications. Thispaper describes the design of a 3-GHz phase-locked loop (PLL) fabricated in a partially-scaled 0.1-pm bulk CMOS technology [l]. The circuit employs anumber of techniques to allow operationfroma low supply voltage and overcome the limitationsdueto device layout rules described below. In order to improve the yield and reduce the turnaround time and cost, the CMOS process used herescalesonly the channel 0Keywords
This publication has 3 references indexed in Scilit:
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- A 200-MHz CMOS phase-locked loop with dual phase detectorsIEEE Journal of Solid-State Circuits, 1989