ESD–RF co-design methodology for the state of the art RF-CMOS blocks
- 1 February 2005
- journal article
- Published by Elsevier in Microelectronics Reliability
- Vol. 45 (2) , 255-268
- https://doi.org/10.1016/j.microrel.2004.05.013
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- High frequency characterization and modelling of the parasitic RC performance of two terminal ESD CMOS protection devicesMicroelectronics Reliability, 2003
- Cancellation technique to provide ESD protection for multi-GHz RF inputsElectronics Letters, 2003
- Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 μm CMOS processPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A study of parasitic effects of ESD protection on RF ICsIEEE Transactions on Microwave Theory and Techniques, 2002
- Analysis and optimization of distributed ESD protection circuits for high-speed mixed-signal and RF applicationsMicroelectronics Reliability, 2002
- High-performance 5.2 GHz LNA with on-chip inductorto provide ESD protectionElectronics Letters, 2001