Can test length be reduced during synthesis process?
- 1 January 1991
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Conventional multi-level logic synthesis is targeted to reduce the area of the logic circuits (estimated via literal count). This paper looks at multi-level combinational logic synthesis from the objective of minimizing test length, i.e. the size of a test set to detect all irredundant single stuck-at faults in the circuit. The length of a test set affects the test application cost. The synthesis process has been modified to obtain circuits that can be tested with smaller test length. Results of the implementation have shown significant reduction in test length with little increase in run time over the MIS-II synthesis system and very little increase in literal count.Keywords
This publication has 7 references indexed in Scilit:
- Fault partitioning issues in an integrated parallel test generation/fault simulation environmentPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Synthesis of delay fault testable combinational logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- SYLON-DREAM: a multi-level network synthesizerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- A dynamic programming approach to the test point insertion problemPublished by Association for Computing Machinery (ACM) ,1987
- On the Complexity of Estimating the Size of a Test SetIEEE Transactions on Computers, 1984
- Test Point Placement to Simplify Fault DetectionIEEE Transactions on Computers, 1974