Increasing energy efficiency of embedded systems by application-specific memory hierarchy generation

1 January 2000

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers

Vol. 17 (2) , 74-85
https://doi.org/10.1109/54.844336

Abstract

This article presents a methodology for automatic memory hierarchy generation that exploits memory access locality of embedded software. The methodology is successfully applied to the design of an MP3 decoder.

Keywords

This publication has 5 references indexed in Scilit:

Energy optimization of multilevel cache architectures for RISC and CISC processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1998
CACTI: an enhanced cache access and cycle time model
IEEE Journal of Solid-State Circuits, 1996
Memory Segmentation to Exploit Sleep Mode Operation
Proceedings of the 39th conference on Design automation - DAC '02, 1995
A tutorial on MPEG/audio compression
IEEE MultiMedia, 1995
Cache performance of the SPEC92 benchmark suite
IEEE Micro, 1993