Energy optimization of multilevel cache architectures for RISC and CISC processors
- 1 June 1998
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 6 (2) , 299-308
- https://doi.org/10.1109/92.678891
Abstract
In this paper, we present the characterization and design of energy-efficient, on chip cache memories. The characterization of power dissipation in on-chip cache memories reveals that the memory peripheral interface circuits and bit array dissipate comparable power. To optimize performance and power in a processor's cache, a multidivided module (MDM) cache architecture is proposed to conserve energy in the bit array as well as the memory peripheral circuits. Compared to a conventional, nondivided, 16-kB cache, the latency and power of the MDM cache are reduced by a factor of 1.9 and 4.6, respectively. Based on the MDM cache architecture, the energy efficiency of the complete memory hierarchy is analyzed with respect to cache parameters in a multilevel processor cache design. This analysis was conducted by executing the SPECint92 benchmark programs with the miss ratios for reduced instruction set computer (RISC) and complex instruction set computer (CISC) machines.Keywords
This publication has 11 references indexed in Scilit:
- On the inclusion properties for multi-level cache hierarchiesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Techniques to reduce power in fast wide memories [CMOS SRAMs]Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Tradeoffs in two-level on-chip cachingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- 1-V, 30-MHz memory-macrocell-circuit technology with a 0.5-μm multi-threshold CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Trends in low-power RAM circuit technologiesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An analytical access time model for on-chip cache memoriesIEEE Journal of Solid-State Circuits, 1992
- A case for direct-mapped cachesComputer, 1988
- A 25-ns low-power full-CMOS 1-Mbit (128 K*8) SRAMIEEE Journal of Solid-State Circuits, 1988
- An 11ns 8k x 18 Cmos Static RamPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- Cache MemoriesACM Computing Surveys, 1982