Using a VHDL description to generate hardware test

This publication has 7 references indexed in Scilit:

• Linking design and test tools: an implementation
  IEEE Transactions on Industrial Electronics, 1989
• Chip-level modeling with HDLs
  IEEE Design & Test of Computers, 1988
• A Heuristic Chip-Level Test Generation Algorithm
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1986
• CATA: A Computer-Aided Test Analysis System
  IEEE Design & Test of Computers, 1984
• Test Generation Algorithms for Computer Hardware Description Languages
  IEEE Transactions on Computers, 1982
• A Unification Algorithm for Associative-Commutative Functions
  Journal of the ACM, 1981
• Confluent Reductions: Abstract Properties and Applications to Term Rewriting Systems
  Journal of the ACM, 1980