System-level modeling and verification: a comprehensive design methodology

This publication has 10 references indexed in Scilit:

• An efficient tool for system-level verification of behaviors and temporal properties
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• A methodology for system-level design for verifiability
  Published by Springer Nature ,1993
• An action based framework for verifying logical and behavioural properties of concurrent systems
  Published by Springer Nature ,1992
• Biting the silver bullet: toward a brighter future for system development
  Computer, 1992
• The Design of Communicating Systems
  Published by Springer Nature ,1991
• Design for verifiability
  Published by Springer Nature ,1990
• Automatic Verification of Sequential Circuits Using Temporal Logic
  IEEE Transactions on Computers, 1986
• Testing equivalences for processes
  Theoretical Computer Science, 1984
• Design for Testability—A Survey
  IEEE Transactions on Computers, 1982
• A Calculus of Communicating Systems
  Lecture Notes in Computer Science, 1980