Design for packageability-the impact of bonding technology on the size and layout of VLSI dies

This publication has 4 references indexed in Scilit:

• Performance modeling of a cache system with three interconnect technologies: cyanate ester PCB, chip-on-board and Cu/PI MCM
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• An integrated CAD system for algorithm-specific IC design
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
• Packaging Architecture Considerations of High Density Multi-Chip Electronic Packages Via System Optimization
  Journal of Electronic Packaging, 1990
• A system-level circuit model for multi- and single-chip CPUs
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1987