A CMOS/SOS 4K static RAM
- 1 October 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 13 (5) , 664-669
- https://doi.org/10.1109/JSSC.1978.1051116
Abstract
Discusses high density CMOS/SOS technology used to develop a fully static 4096-bit RAM with a five-transistor storage cell. Selection of a five-transistor memory cell has reduced the access to the flip-flop storage element to a single word line transistor and bit line. The word line transistor must be able to prevent data altering currents from entering the memory cell at all times except for the write operation. The write operation is enhanced by reducing the bias voltage across the memory cell, thereby making the current needed to alter the cell smaller. Through the use of a 5 /spl mu/m design rule, the memory cell occupies 2913 /spl mu/m/SUP 2/. The 4096-bit static CMOS/SOS RAM contains 22553 transistors in 20 mm/SUP 2/. Organised as 1024 4-bit words, the RAM has a read cycle time of 350 ns and standby power dissipation of 50 /spl mu/W at V/SUB cc/=5 V and temperature of 27/spl deg/C.Keywords
This publication has 4 references indexed in Scilit:
- Two 4K static 5-V RAM'sIEEE Journal of Solid-State Circuits, 1976
- Five-transistor memory cells in ESFI MOS technologyIEEE Journal of Solid-State Circuits, 1973
- A 4K MOS dynamic random-access memoryIEEE Journal of Solid-State Circuits, 1973
- High-performance low-power CMOS memories using silicon-on-sapphire technologyIEEE Journal of Solid-State Circuits, 1972