Output characteristics of short-channel polycrystalline silicon thin-film transistors

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Abstract
An analytical model for the turn-on current-voltage characteristics of polycrystalline silicon thin-film transistors is presented. The model is based on the drift diffusion-thermionic emission conduction mechanisms and on a continuous distribution in the energy gap of the traps localized at the grain boundaries. The trap distribution and the device parameters involved in the model are determined by fitting the calculated on-state current versus gate voltage curve to the measured one in the linear region. At large drain voltage, the barrier height at the grain boundary becomes asymmetric and the injection of carriers from the lowered barrier side of the boundary is increased resulting in an exponential increase of the drain current with the drain voltage. Using the parameters obtained from the data in the linear region, the output characteristics are calculated. The good agreement between calculated results and experimental data at room temperature and at higher temperatures demonstrates the validity of the proposed current-voltage model.