Perfect-balance planar clock routing with minimal path-length
- 1 January 1992
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
In the design of high speed digital VLSI circuits, it is preferable that the clock net be routed on the metal layer with the smallest RC delay. This strategy not only avoids the difficulties of having different electrical parameters on different layers, but also eliminates the delay and attenuation of the clock signal through vias. The clock phase-delay is also decreased. An algorithm, based on max-min optimization, to construct a planar clock tree which can be embedded on a single metal layer is presented. The clock tree achieves equal path lengths, i.e., the lengths of the paths from the clock source to each clock terminal are exactly the same. In addition, the path length from the source to clock terminals is minimized. Some examples including industrial benchmarks have been tested, and the results are promising.Keywords
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