Area and delay mapping for table-look-up based field programmable gate arrays
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 368-373
- https://doi.org/10.1109/dac.1992.227776
Abstract
In this paper we present a new app?’each to technology mapping foT aTea and delay for truth table based Field PTogI’ammabie Gate Arrays. We view the area and delay optimization duTing technology mapping as a case of clique partitioning foT which we have developed an eficient heuTistic. Additionally, we also expioTe alternate decompositions using Shannon Expansion. Experimental results indicate that on the average OUT algoriihm foT area optimization performs 10% - 19% better compared to pTevious approaches [3, 6]. OUT approach to delay optimization on the average p?’educes 3% feweT numbeT of levels with 44% less aTea compared to other approaches [4].Keywords
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