Validatable nonrobust delay-fault testable circuits via logic synthesis
- 1 December 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 11 (12) , 1559-1573
- https://doi.org/10.1109/43.180267
Abstract
No abstract availableKeywords
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