A masterslice LSI for subnanosecond random logic
- 1 October 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 14 (5) , 829-832
- https://doi.org/10.1109/JSSC.1979.1051279
Abstract
Describes the design and implementation of a bipolar subnanosecond gate arrays with a complexity up to 700 gates. There are three different basic arrays with either 24 or 36 cells or 24 cells plus a 128 bit RAM. Each cell has the logic power of a small MSI. The masterslice is ECL compatible.Keywords
This publication has 3 references indexed in Scilit:
- A masterslice LSI for subnanosecond random logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977
- Bipolar high-speed low-power gates with double implanted transistorsIEEE Journal of Solid-State Circuits, 1975
- Large-Signal Behavior of Junction TransistorsProceedings of the IRE, 1954