ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS — Implementation concepts, constraints and solutions
- 1 September 2004
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Design and implementation of ESD protection for a 5.5 GHz Low Noise Amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as ldquoplug-and-playrdquo, is used as ESD protection for the RF pins. The consequences of design and process, as well as the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail and additional improvements are suggested.Keywords
This publication has 6 references indexed in Scilit:
- Comprehensive ESD protection for RF inputsMicroelectronics Reliability, 2005
- Low-power 5 GHz LNA and VCO in 90 nm RF CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Weibull slope and voltage acceleration of ultra-thin (1.1–1.45 nm EOT) oxynitridesMicroelectronic Engineering, 2004
- Design-driven optimisation of a 90 nm RF CMOS process by use of elevated source/drainPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- High-performance 5.2 GHz LNA with on-chip inductorto provide ESD protectionElectronics Letters, 2001
- A 1.5-V, 1.5-GHz CMOS low noise amplifierIEEE Journal of Solid-State Circuits, 1997