VLSI implementation of synaptic weighting and summing in pulse coded neural-type cells
- 1 May 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Neural Networks
- Vol. 3 (3) , 394-403
- https://doi.org/10.1109/72.129412
Abstract
Presents the hardware realization for synaptic weighting and summing using pulse-coded neural-type cells (NTCs). The basic information processing element (NTC) encodes the information into the form of pulse duty cycles using voltage-controlled resistors, for which a pulse duty cycle modulation technique is proposed. Summation is executed by a simple capacitor circuit as a current integrator. Layouts and measurements on a fabricated integrated design are included.<>Keywords
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