Spacer FinFET: nano-scale CMOS technology for the terabit era
- 13 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A spacer lithography process technology using a sacrificial layer and a CVD (Chemical Vapor Deposition) spacer layer has been developed, and is demonstrated to achieve sub-40 nm structures with conventional dry etching. The minimum-sized features are defined not by photolithography but by the CVD film thickness. Therefore the spacer lithography technology yields CD (Critical Dimension) variations of minimum-sized features which are much smaller than achieved by optical or e-beam lithography. It also provides a doubling of device density for a given lithography pitch. This spacer lithography technology is used to pattern Si-fin structures for double-gate MOSFETs (FinFETs), and CMOS FinFET results are reported.Keywords
This publication has 5 references indexed in Scilit:
- Patterning sub-30-nm MOSFET gate with i-line lithographyIEEE Transactions on Electron Devices, 2001
- FinFET-a self-aligned double-gate MOSFET scalable to 20 nmIEEE Transactions on Electron Devices, 2000
- Ultrathin-body SOI MOSFET for deep-sub-tenth micron eraIEEE Electron Device Letters, 2000
- CMOS scaling into the nanometer regimeProceedings of the IEEE, 1997
- Selective chemical etching of polycrystalline SiGe alloys with respect to Si and SiO2Journal of Electronic Materials, 1992