A defect relaxation model for bias instabilities in metal-oxide-semiconductor capacitors
- 15 August 1988
- journal article
- Published by AIP Publishing in Journal of Applied Physics
- Vol. 64 (4) , 2221-2223
- https://doi.org/10.1063/1.341688
Abstract
We have studied electron trapping and detrapping resulting from bias stress applied to a metal-sputtered oxide-native oxide-semiconductor capacitor. The trapping process is described as band-to-trap tunneling. Based on the assumption of a trap with a delta function spatial distribution, a model was developed that predicts a trap energy distribution and defect relaxation energy. Application of this model to experimental data reveals a value for the relaxation energy of approximately 1 eV. We suggest that this model may apply to hysteretic instabilities observed in p-channel transistors and dual dielectric memory devices.This publication has 8 references indexed in Scilit:
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