Shared binary decision diagram with attributed edges for efficient Boolean function manipulation

This publication has 6 references indexed in Scilit:

• Proving circuit correctness using formal comparison between expected and extracted behaviour
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Logic verification using binary decision diagrams in a logic synthesis environment
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Evaluation and improvement of Boolean comparison method based on binary decision diagrams
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Test pattern generation for sequential MOS circuits by symbolic fault simulation
  Published by Association for Computing Machinery (ACM) ,1989
• Graph-Based Algorithms for Boolean Function Manipulation
  IEEE Transactions on Computers, 1986
• Binary Decision Diagrams
  IEEE Transactions on Computers, 1978