A 16 ns 2Kx8 bit full CMOS SRAM
- 1 October 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 19 (5) , 552-556
- https://doi.org/10.1109/jssc.1984.1052188
Abstract
A high-speed 2K/spl times/8 bit full CMOS SRAM fabricated with a platinum silicide gate electrode and single-level aluminum technology is described. A typical address access time of 16 ns, which is comparable to the 16-kb bipolar SRAMs, was achieved. Typical active and standby power dissipations are 150 mW and 25 nW, respectively. The platinum silicide word line reduces the total address access time by 25%. A compact cell layout design, as well as a 1.5-/spl mu/m device feature size, also gives fast access time. The properly controlled bit line swing voltage provides reliable and fast readout operation. The chip size of the SRAM is 2.7/spl times/3.5 mm.Keywords
This publication has 3 references indexed in Scilit:
- A 35 ns 2K x 8 HMOS static RAMIEEE Journal of Solid-State Circuits, 1983
- A HI-CMOSII 8K × 8b static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- A 15nW standby power 64Kb CMOS RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982