Multiple word/bit line redundancy for semiconductor memories
- 1 October 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 13 (5) , 698-703
- https://doi.org/10.1109/jssc.1978.1051122
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
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- Experimental study of laser formed connections for LSI wafer personalizationIEEE Journal of Solid-State Circuits, 1975
- Monolithic main memoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1971
- A fully-decoded 2048-bit electrically-programmable MOS ROMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1971
- Redundancy in LSI memory arrayIEEE Journal of Solid-State Circuits, 1969
- Redundancy for LSI Yield EnhancementIEEE Journal of Solid-State Circuits, 1967