Redundancy removal and simplification of combinational circuits
- 2 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Redundancy in combinational circuits is usually identified when faults are found to be undetectable during test generation. Redundancy removal based on test generation is not efficient, because removal of the redundancy causing a fault to be undetectable will usually affect the detectability of other faults, making it necessary to repeat test generation. The authors present a method of identifying and removing redundancy in combinational circuits by analyzing regions between fanout stems and reconvergence gates, and experimental results for the ISCAS85 benchmark circuits.Keywords
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