Optimization of silicon bipolar transistors for high current gain at low temperatures
Open Access
- 1 August 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 35 (8) , 1311-1321
- https://doi.org/10.1109/16.2553
Abstract
No abstract availableKeywords
This publication has 25 references indexed in Scilit:
- Substrate current at cryogenic temperatures: Measurements and a two-dimensional model for CMOS technologyIEEE Transactions on Electron Devices, 1987
- Physics, technology, and modeling of polysilicon emitter contacts for VLSI bipolar transistorsIEEE Transactions on Electron Devices, 1986
- CMOS/bipolar circuits for 60-MHz digital processingIEEE Journal of Solid-State Circuits, 1986
- Majority and minority carrier transport in polysilicon emitter contactsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- Advanced BiCMOS technology for high speed VLSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- Temperature dependence of latchup in CMOS circuitsIEEE Electron Device Letters, 1984
- VLSI Process modeling—SUPREM IIIIEEE Transactions on Electron Devices, 1983
- Miniaturization of Si MOSFET's at 77 KIEEE Transactions on Electron Devices, 1982
- Effect of scaling of interconnections on the time delay of VLSI circuitsIEEE Transactions on Electron Devices, 1982
- Bipolar transistor design for optimized power-delay logic circuitsIEEE Journal of Solid-State Circuits, 1979