A two-terminal transistor memory cell using breakdown
- 1 October 1971
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 6 (5) , 280-283
- https://doi.org/10.1109/JSSC.1971.1050187
Abstract
The features of the cell include easy fabrication, small cell area, large output signals, high-speed Read and Write capability, low average power and inherent immunity to small voltage perturbations. The storage time of the cell is determined by reverse-bias junction leakage and is greater than 10 ns at room temperatures for typical devices. Breakdown degradation of transistors is discussed and a memory fabrication scheme that avoids this degradation is suggested. Some early experimental results are mentioned.Keywords
This publication has 6 references indexed in Scilit:
- Avalanche degradation of hFEIEEE Transactions on Electron Devices, 1970
- On the mechanism of hFE degradation by emitter-base reverse current stressMicroelectronics Reliability, 1970
- AVALANCHE INJECTION CURRENTS AND CHARGING PHENOMENA IN THERMAL SiO2Applied Physics Letters, 1969
- hFEdegradation due to reverse bias emitter-base junction stressIEEE Transactions on Electron Devices, 1969
- Degradation Phenomena of Planar Si Devices Due to Surface and Bulk EffectsFourth Annual Symposium on the Physics of Failure in Electronics, 1967
- Effect of junction curvature on breakdown voltage in semiconductorsSolid-State Electronics, 1966