Effects of the presence/absence of HCl during gate oxidation on the electrical and structural properties of polycrystalline silicon thin-film transistors

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Abstract
The influence of the presence or absence of HCl during gate oxidation at 1100 and 1150 °C on the electrical and structural properties of polycrystalline silicon thin-film transistors was investigated. Devices processed without HCl exhibited a lower leakage current, a larger current switching ratio, a 25%–55% increase in carrier mobility, and a 21%–30% lower grain-boundary trap density. Materials investigation showed that the improvement was not primarily due to an increase in grain size, which was about 1000 Å irrespective of processing conditions, but to a change in crystallite orientation. X-ray diffraction measurements showed an increased {110} texture in devices processed without HCl. In addition, in the latter devices, dopant diffusion under the gate from the source and drain contacts was reduced by 7.6% to 12%. A linear relationship was observed between the average grain-boundary trap density and the average lateral dopant diffusion length. These findings are explained by considering the point defect chemistry and its relationship to grain-boundary mobility. Removal of HCl from the oxidation ambient increases the concentration of silicon self-interstitials. The increased migration of these point defects to grain boundaries enhances their nonconservative motion and therefore increases grain-boundary mobility. This in turn, allows the boundary to more completely acquire a lower-energy configuration. This lower-energy configuration of the boundary contains a minimum of broken bonds and therefore minimizes both the grain-boundary electrical activity and the diffusion along grain boundaries.