A high-speed low-power 4096 x 1 bit bipolar RAM
- 1 October 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 13 (5) , 651-656
- https://doi.org/10.1109/JSSC.1978.1051114
Abstract
Describes a 4096-word by 1-bit TTL static bipolar RAM with a typical address access time of 25 ns and power dissipation of 350 mW. Emphasis is given to circuit techniques which made the high performance possible. These techniques are: variable impedance cell (VIC) with low standby current capable of fast switching of digit lines, cell margin increasing circuitry which increases the operating margin of the cell with low standby current, sharing of only one pair of read current sources by 64 pairs of digit lines, and Darlington word drivers causing fast switching of word lines. The process and device structure are mentioned briefly.Keywords
This publication has 4 references indexed in Scilit:
- A static 4096-bit bipolar random-access memoryIEEE Journal of Solid-State Circuits, 1977
- A high performance 4K static RAM fabricated with an advanced MOS technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977
- A 4096 x 1 static bipolar RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977
- A 1024-bit ECL RAM with 15-ns access timePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1976