Memory SEU simulations using 2-D transport calculations
- 1 August 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 6 (8) , 422-424
- https://doi.org/10.1109/edl.1985.26177
Abstract
An advance in the simulation of a single event upset (SEU) of a static memory is achieved by combining transport and circuit effects in a single calculation. The program SIFCOD [4] is applied to the four transistors of a CMOS SRAM cell to determine its transient circuit response following a very high energy ion hit. Results unique to this type of calculation include determination of relative upset sensitivites and different upset mechanisms for specific area hits, i.e., the OFF p-channel drain, the OFF or ON n-channel drain, etc. The calculation determines the transport variables as a function of time in two-space dimensions for each of the four transistors and provides the nodal voltage and current responses for assessing memory upset conditions.Keywords
This publication has 5 references indexed in Scilit:
- Dominant subthreshold conduction paths in short-channel MOSFET'sIEEE Transactions on Electron Devices, 1984
- Charge Collection in Multilayer StructuresIEEE Transactions on Nuclear Science, 1984
- Two-Dimensional Simulation of Single Event Indujced Bipolar Current in CMOS StructuresIEEE Transactions on Nuclear Science, 1984
- Comparison of Analytical Models and Experimental Results for Single Event Upset in CMOS SRAMsIEEE Transactions on Nuclear Science, 1983
- A field-funneling effect on the collection of alpha-particle-generated carriers in silicon devicesIEEE Electron Device Letters, 1981