A 64-entry 167 MHz fully-associative TLB for a RISC microprocessor
- 23 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Memory subsystems of RISC microprocessors require efficient translation of virtual addresses to physical addresses. A fully-associative embedded translation lookaside buffer (TLB) provides this function in a microprocessor. Two identical TLBs are used: one for instructions and another for data. The CPU architecture requires that the TLB translate a new address every cycle.Keywords
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