Equivalence of robust delay-fault and single stuck-fault test generation
- 2 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 173-176
- https://doi.org/10.1109/dac.1992.227841
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- Advanced automatic test pattern generation techniques for path delay faultsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Advanced automatic test pattern generation and redundancy identification techniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Timing analysis and delay-fault test generation using path-recursive functionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On the design of path delay fault testable combinational circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Random pattern testability of delay faultsIEEE Transactions on Computers, 1988