Analysis of Drain Field and Hot Carrier Stability of Poly-Si Thin Film Transistors

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Abstract
Hot carrier instabilities in poly-Si thin film transistors (TFTs) are caused by high electric fields at the drain. These high fields are determined mainly by the abruptness of the lateral n+ doping profile in the drain and the two-dimensional (2D) coupling of the x and y components of the electric field between the gate and drain. The density of trapping states in the poly-Si film, however, has a much less significant impact on the field. Further, it is shown that improving the properties of the poly-Si film tends to have an adverse affect on hot carrier stability. Consequently, it is concluded that drain field relief is essential for hot carrier stability of n-channel poly-Si TFTs. It is shown that gate overlapped lightly doped drain (GOLDD) architectures can be used to relieve the drain field without introducing series resistance. Stable TFTs have been fabricated with GOLDD, consistent with circuit operation up to drain biases of 20 V. GOLDD is also effective in reducing the field enhanced leakage current in the off-state.