A Gate Level Model for CMOS Combinational Logic Circuits with Application to Fault Detection
- 1 January 1984
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 0738100X,p. 504-509
- https://doi.org/10.1109/dac.1984.1585845
Abstract
A procedure to derive gate level equivalent circuits for CMOS combinational logic circuits is given. The procedure leads to a model containing AND, OR and NOT gates. Specifically it does not require memory elements as does an earlier model and also uses fewer gates. It is shown that tests for classical stuck-at-0 and stuck-at-1 faults in the equivalent circuit can be used to detect line stuck-at, stuck-open and stuck-on faults in the modeled CMOS circuit.Keywords
This publication has 9 references indexed in Scilit:
- Fault Detection and Design For Testability of CMOS Logic CircuitsPublished by Springer Nature ,1988
- Test Generation for MOS Circuits Using D-AlgorithmPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- On Fault Detection in CMOS Logic NetworksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Design for Autonomous TestIEEE Transactions on Computers, 1981
- Automatic Test Generation for Stuck-Open Faults in CMOS VLSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their TestabilityIEEE Transactions on Computers, 1980
- CMOS LSI Special Feature: CMOS LSI – Computer Component Process of the 80'sComputer, 1980
- Fault Modeling and Logic Simulation of CMOS and MOS Integrated CircuitsBell System Technical Journal, 1978
- Diagnosis & Reliable Design of Digital SystemsPublished by Springer Nature ,1976