Fast multiplication in VLSI using wave pipelining techniques

This publication has 12 references indexed in Scilit:

• Use of CMOS Technology in Wave Pipelining
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
• A 54*54-b regularly structured tree multiplier
  IEEE Journal of Solid-State Circuits, 1992
• A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequency
  IEEE Journal of Solid-State Circuits, 1992
• Circuit and architecture trade-offs for high-speed multiplication
  IEEE Journal of Solid-State Circuits, 1991
• A 15-ns 32*32-b CMOS multiplier with an improved parallel structure
  IEEE Journal of Solid-State Circuits, 1990
• The design and implementation of a very fast experimental pipelining computer
  Journal of Computer Science and Technology, 1988
• A Regular Layout for Parallel Adders
  IEEE Transactions on Computers, 1982
• The IBM System/360 Model 91: Floating-Point Execution Unit
  IBM Journal of Research and Development, 1967
• A Suggestion for a Fast Multiplier
  IEEE Transactions on Electronic Computers, 1964