Performance estimation of Si/SiGe hetero-CMOS circuits

30 January 1997

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 33 (3) , 208-210
https://doi.org/10.1049/el:19970166

Abstract

Semiquantitative performance extrapolation of Si/SiGe heterostructure p- and n-channel devices point to transconductances above 1000 mS/mm and cutoff frequencies around 200 GHz. Circuits such as inverters, logic arrays (e.g. NAND-gates) and flip-flops are simulated with feature sizes down to 0.05 µm showing a promising performance potential. Delay times of 2.5 and 0.5 ps/stage are obtained for an inverter chain at a power supply voltage of 1 and 2.5 V, respectively.

Keywords

This publication has 5 references indexed in Scilit:

High speed p-type SiGe modulation-doped field-effect transistors
IEEE Electron Device Letters, 1996
Design of Si/SiGe heterojunction complementary metal-oxide-semiconductor transistors
IEEE Transactions on Electron Devices, 1996
Electron transport properties of Si/SiGe heterostructures: Measurements and device implications
Applied Physics Letters, 1993
High-performance Si/SiGe n-type modulation-doped transistors
IEEE Electron Device Letters, 1993
GaAs FET device and circuit simulation in SPICE
IEEE Transactions on Electron Devices, 1987