Dynamic asynchronous logic for high-speed CMOS systems

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Abstract
As transistor switching speed improves, synchronizing a global clock increasingly degrades system performance. Therefore, self-timed asynchronous logic becomes potentially faster than synchronous logic. To do so, however, it must exploit the techniques used in fast synchronous designs, including: redundant logic, inverting logic, transistor size optimization, dynamic logic, and phase alignment. Most techniques can be applied equally well to asynchronous logic, indeed phase alignment is easier; but combining dynamic and asynchronous logic is more difficult. We must guarantee minimum refresh intervals, together with race and hazard free operation. This paper describes an initial chip implementation, that combines dynamic and asynchronous logic running at 500MHz in 2 μm CMOS. With the addition of transistor size optimization, simulations show the same circuit running in the same technology at 800MHz.

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