A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution

28 June 2004

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits

Vol. 39 (7) , 1056-1063
https://doi.org/10.1109/jssc.2004.829925

Abstract

A wide-bandwidth continuous-time sigma-delta ADC is implemented in a 0.13-/spl mu/m CMOS. The circuit is targeted for wide-bandwidth applications such as video or wireless base-stations. The active blocks are composed of regular threshold voltage devices only. The fourth-order architecture uses an OpAmp-RC-based loop filter and a 4-bit internal quantizer operated at 300-MHz clock frequency. The converter achieves a dynamic range of 11 bits over a bandwidth of 15 MHz. The power dissipation is 70 mW from a 1.5-V supply.

Keywords

This publication has 8 references indexed in Scilit:

Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2004
Influence of finite integrator gain bandwidth on continuous-time sigma delta modulators
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture
IEEE Journal of Solid-State Circuits, 2003
A 700/900mW/channel CMOS dual analog front-end IC for VDSL with integrated 11.5/14.5dBm line drivers
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC
IEEE Journal of Solid-State Circuits, 2000
A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio
IEEE Journal of Solid-State Circuits, 2000
A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC
IEEE Journal of Solid-State Circuits, 2000
Delta-Sigma Data Converters
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1996