A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio
- 1 December 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 35 (12) , 1820-1828
- https://doi.org/10.1109/4.890295
Abstract
A 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications and high-speed instrumentation has been developed. A 2-1-1 cascaded delta-sigma modulator (DSM) employing 4-b quantizers in every stage makes all quantization noise sources negligible at 8/spl times/ oversampling ratio, Data weighted averaging with bi-directional rotation eliminates tones generated by multibit digital-to-analog converter (DAC) nonlinearity to increase the spurious-free dynamic-range (SFDR). Switched-capacitor design techniques using low-threshold transistors reduce front-end sampling distortion. The 24.8 mm/sup 2/ chip in 0.5-/spl mu/m CMOS also integrates the decimation filter and voltage reference. The ADC achieves 90-dB signal-to-noise ratio (SNR) in the 1.25-MHz bandwidth and 102-dB SFDR with 270-mW power dissipation.Keywords
This publication has 18 references indexed in Scilit:
- A multi-bit ΔΣ audio DAC with 120 dB dynamic rangePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applicationsIEEE Journal of Solid-State Circuits, 1999
- A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technologyIEEE Journal of Solid-State Circuits, 1999
- Resonance and damping in CMOS circuits with on-chip decoupling capacitanceIEEE Transactions on Circuits and Systems I: Regular Papers, 1998
- A 5-V single-chip delta-sigma audio A/D converter with 111 dB dynamic rangeIEEE Journal of Solid-State Circuits, 1997
- Noise-shaped multbit D/A convertoremploying unit elementsElectronics Letters, 1995
- Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averagingIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1995
- A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversionIEEE Journal of Solid-State Circuits, 1991
- A third-order multistage sigma-delta modulator with reduced sensitivity to nonidealitiesIEEE Journal of Solid-State Circuits, 1991
- Improvement of the gain of MOS amplifiersIEEE Journal of Solid-State Circuits, 1979