Easily testable iterative unidimensional CMOS circuits
- 7 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 240-245
- https://doi.org/10.1109/etc.1989.36249
Abstract
No abstract availableKeywords
This publication has 12 references indexed in Scilit:
- Detecting FET Stuck-Open Faults in CMOS Latches And Flip-FlopsIEEE Design & Test of Computers, 1986
- Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic CircuitsIEEE Transactions on Computers, 1986
- Algorithms for Iterative Array MultiplicationIEEE Transactions on Computers, 1986
- Built-In Testing of One-Dimensional Unilateral Iterative ArraysIEEE Transactions on Computers, 1984
- Design of Easily Testable Bit-Sliced SystemsIEEE Transactions on Computers, 1981
- A Functional Approach to Testing Bit-Sliced MicroprocessorsIEEE Transactions on Computers, 1981
- Fault Modeling and Logic Simulation of CMOS and MOS Integrated CircuitsBell System Technical Journal, 1978
- Truth-Table Verification of an Iterative Logic ArrayIEEE Transactions on Computers, 1976
- Easily Testable Iterative SystemsIEEE Transactions on Computers, 1973
- Testing for faults in combinational cellular logic arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1967