Delay optimization of digital CMOS VLSI circuits by transistor reordering
- 1 January 1995
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 14 (10) , 1183-1192
- https://doi.org/10.1109/43.466335
Abstract
In this paper the effects of transistor reordering on the delay of CMOS digital circuits are investigated, and an efficient method which uses transistor reordering for the delay optimization of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect an layout area and power dissipation, The technique can be coupled with transistor sizing to achieve the desired improvement in circuit delay. Experimental results for benchmark circuits are given in 2.0, 1.2, and 0.8 mu m CMOS technologies. The average improvement in delay for the 20 benchmarks used in this paper is 9.1%.This publication has 16 references indexed in Scilit:
- A timing model for static CMOS gatesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Pin assignment for improved performance in standard cell designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Experiments using automatic physical design techniques for optimizing circuit performancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Synchronous-mode evaluation of delays in CMOS structuresIEEE Journal of Solid-State Circuits, 1991
- Delay analysis of series-connected MOSFET circuitsIEEE Journal of Solid-State Circuits, 1991
- The interdependence between delay-optimization of synthesized networks and testingPublished by Association for Computing Machinery (ACM) ,1991
- Optimization-based transistor sizingIEEE Journal of Solid-State Circuits, 1988
- Aesop: a tool for automated transistor sizingPublished by Association for Computing Machinery (ACM) ,1987
- Delay Reduction Using Simulated AnnealingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- Algorithms for Automatic Transistor Sizing in CMOS Digital CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985